Curvilinear OPC Application On 180nm Silicon Photonics Layout For Better Performance

Curvilinear OPC Application On 180nm Silicon Photonics Layout For Better Performance

This Advanced silicon photonics (SiPho) device design requires RET OPC technology to increase manufacturability. However, the traditional OPC solution can't handle SiPho design very well because of the skew edges. The Inverse Lithography Technology (ILT) is an alternative way to do however this...

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Bibliographic Details
Published in:2022 International Workshop on Advanced Patterning Solutions (IWAPS) pp. 1 - 3
Main Authors: Wu, Qing, Li, Zhifeng, Zhu, Cynthia, Peng, Lulu, Jin, Yadong, Shao, Feng, Lippincott, George, Liubich, Vlad, Cao, Guowei, Sandhu, Avneet
Format: Conference Proceeding
Language:English
Published: IEEE 21-10-2022
Subjects:
Calibre nmCLOPC
Computational modeling
Conferences
Full-chip
Inverse lithography technology
Layout
Lithography
Performance evaluation
pxOPC
Runtime
Semiconductor device modeling
Silicon photonics
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Summary:This Advanced silicon photonics (SiPho) device design requires RET OPC technology to increase manufacturability. However, the traditional OPC solution can't handle SiPho design very well because of the skew edges. The Inverse Lithography Technology (ILT) is an alternative way to do however this solution suffers a very long runtime for the full-chip run. We applied a new full chip Curvilinear (CL) OPC solution which is designed for Curvilinear layout. It is proven that CLOPC can be used for full-chip photonics designs with good device performance. This paper will introduce the application of curvilinear OPC on 180nm silicon photonics layouts.
DOI:10.1109/IWAPS57146.2022.9972328