Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design

• Published in: 2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 4
• Main Authors: Gupta, Yatin Kumar, Agrawal, Yash, Parekh, Rutu, Gohel, Bakul
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-09-2021
• Subjects: Edge traffic distribution (ETD); Graphene; integrated circuit (IC); Integrated circuit interconnections; Integrated circuit synthesis; interconnects; Network-on-chip; network-on-chip (NoC); system-on-chip (SoC); Very large scale integration; Wiring
• DOI: 10.1109/VDAT53777.2021.9601133

Network-on-chip (NoC) has evolved as new paradigm for high-dense interconnect configurations in advanced integrated circuit designs. The increasing number of transistor cores with decrease in chip area is the leading motivation behind employment of NoC over system-on-chip (SoC) architectures. NoC provides re-configurable interconnections between different cores in the SoC design. It maximizes data transfer speed and reduction in wiring congestion. For further effective performance enhancement of NoCs, it is envisaged that incorporation of graphene material can be good for realizing interconnects. In this paper, edge traffic distribution (ETD) algorithm is explored along with magnificent graphene based interconnects for NoC design. Performance parameters considered are delay, power, energy and throughput. It is investigated that the ETD routing algorithm leads to reduced delay, higher throughput, and smaller packet loss. Further it is analyzed that graphene based NoC leads to smaller energy consumption for the link connecting two routers. The assessment of NoC structures has been performed using Noxim and SPICE electronic design automation tools.