Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory

• Published in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 308 - 309
• Main Authors: Morooka, T., Ishikawa, T., Komura, M., Kato, T., Koyama, Y., Han, Y., Sugawara, Y., Kuwabara, D., Arayashiki, Y., Murayama, A., Nishiyama, K., Sugimae, K., Ogura, T., Takeda, H., Kariya, N., Goki, Y., Konuma, S., Kamiya, Y., Yamashita, H., Shiga, H., Itagaki, K., Tanaka, R., Maeda, T., Ohtani, N., Fujiwara, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 12-06-2022
• Subjects: Boosting; Flash memories; Leakage currents; Nonvolatile memory; Split gate flash memory cells; Three-dimensional displays; Very large scale integration
• ISSN: 2158-9682
• DOI: 10.1109/VLSITechnologyandCir46769.2022.9830513

Three-dimensional (3D) semicircular split-gate floating-gate (FG) cells have been successfully developed for both boosting cell density per footprint and expanding the capability of multiple bits per cell. FG structure engineering mitigates program/erase (P/E) window reduction due to the fringing field effect in the split-gate cell. Front-side and back-side cells which share the same channel can be separately read by reducing back-side cell leakage current by means of back-gate bias control. Moreover, FG structure enables tight V th distribution by suppressing random telegraph noise (RTN) increase due to small cell area. As a result, the distributions of four bits/cell (QLC) and five bits/cell (PLC) have been experimentally demonstrated by the split-gate cell arrays for the first time.