Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation

• Published in: 2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 4
• Main Authors: Mythrai, Pragna, S, Kavitha, Singh, P., Shah, A. P., Vishwakarma, S. K., Reniwal, B. S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-09-2021
• Subjects: CMOS technology; Codes; Computer architecture; Energy consumption; Hamming code; In-Memory Computing; Power demand; Random access memory; SRAM; Very large scale integration; Von-Neumann Architecture; XOR
• DOI: 10.1109/VDAT53777.2021.9601068

In this work, for the first time, we have proposed and implemented the In-memory computation (IMC) of Hamming code for redundant bit generation(encoding) and syndrome calculation(decoding) with two different design techniques 2 Bit X-or based Hamming code Design (2BxHCD) and Bit Specific X-or based Hamming code Design (BSxHCD) with the 8T static random-access memory (SRAM), in the standard 90nm CMOS technology. The key objective of the proposed techniques is reducing the latency and power consumption to increase the overall performance of the system. The latency of the proposed 2BxHCD and BSxHCD is 1.41× and 1.26× lower than the conventional design, respectively. In comparison to conventional design, power consumption is 6.52× and 3.07× less in proposed 2BxHCD and BSxHCD, respectively. Furthermore, energy consumption which is an important figure of merit (FoM) is 9.45× and 4.08× lower than the conventional Hamming code encoder design.