A General Purpose Hyperdimensional Computing Accelerator for Edge Computing

• Published in: 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS) pp. 383 - 387
• Main Authors: Asghari, Mohsen, Beux, Sebastien Le
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-06-2024
• Subjects: Computer architecture; Edge Computing; FPGA implementation; Hyperdimensional Computing; Image edge detection; Instruction sets; Machine learning; Parallel processing; Performance evaluation; Scalability
• ISSN: 2474-9672
• DOI: 10.1109/NewCAS58973.2024.10666335

Hyperdimensional computing (HDC) is a lightweight machine learning paradigm. Since HDC relies on bitwise operations instead of matrix multiplications, it is commonly used for classification tasks in edge computing devices. For this purpose, numerous hardware architectures have been proposed to accelerate HDC applications. However, existing solutions suffer from a lack of flexibility, which prevents from a deployment of HDC for a wide range of applications. In this paper, we propose a general-purpose HDC accelerator, called GP-HDCA, which is suitable for FPGAs implementation. To enable the efficient implementation of encoders, which is the most critical component in HDC, we define an instruction set tailored to ease the use of the accelerator as a coprocessor. Synthesis results show that our accelerator, configured with a 32-bit integer size and 32-bit vector slice, requires only 7% of the resources available in a Zedboard. Finally, our results show that a 12x speedup is achieved when processing a language detection application, demonstrating the suitability of the architecture for edge computing.