A 10th generation 16-core SPARC64 processor for mission-critical UNIX server

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 60 - 61
• Main Authors: Kan, R., Tanaka, T., Sugizaki, G., Nishiyama, R., Sakabayashi, S., Koyanagi, Y., Iwatsuki, R., Hayasaka, K., Uemura, T., Ito, G., Ozeki, Y., Adachi, H., Furuya, K., Motokurumada, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2013
• Subjects: Backplanes; Decision feedback equalizers; Ground penetrating radar; Latches; Pipelines; Program processors; Reliability
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487637

The 10 th generation SPARC64™ processor named SPARC64 X contains 3-billion transistors on a 588mm 2 die fabricated in an enhanced 28nm high-κ metal-gate (HKMG) CMOS process, with 13 layers of copper interconnect with low-κ dielectrics. More stress control, SiGe improvement and S/D optimization achieve about 10% higher performance than the standard 28nm high performance (28HP) process. SPARC64 X runs at 3.0GHz and consists of 16 cores, shared 24MB level 2 (L2) cache, four channels of 1.6GHz DDR3 controller, two ports of PCIe Gen3 controller, and five ports of system interface controller. ccNUMA is adopted as its memory system, and a cache coherence control unit for multi-chip systems with up to 64 processors is integrated into L2 cache control circuitry for lower latency and reduced area and power consumption.