Silicon Oxide enhanced Schottky gate In0.53Ga0.47As FET's with a self-aligned recessed gate structure

• Published in: IEEE electron device letters Vol. 5; no. 12; pp. 511 - 514
• Main Authors: Cheng, C.L., Liao, A.S.H., Chang, T.Y., Caridi, E.A., Coldren, L.A., Lalevic, B.
• Format: Journal Article
• Language: English
• Published: IEEE 01-12-1984
• Subjects: Electrical resistance measurement; Electron devices; Graphics; Hysteresis; Indium gallium arsenide; Leakage current; Schottky gate field effect transistors; Silicon; Threshold voltage; Transconductance
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/EDL.1984.26008

We present the fabrication and characterization of an In 0.53 Ga 0.47 As enhanced Schottky gate FET with a self-aligned recessed gate structure. A thin layer of e-beam evaporated silicon oxide was used to reduce the gate leakage current. For a n-channel doping of 8 × 10 16 cm -3 and a gate length of 1.5 µm, these devices showed good pinchoff characteristics with transconductances of 150 mS/mm. The effective velocity of electrons at current saturation is deduced to be 2.4 × 10 7 cm/s at the drain end of the gate. At 3 GHz these devices have a maximum available gain of 10 dB, decreasing to 6 dB at 6 GHz.