Low Power Sampling Latch for up to 25 Gb/s 2x Oversampling CDR in 90-nm CMOS

• Published in: 2006 Proceedings of the 32nd European Solid-State Circuits Conference pp. 106 - 109
• Main Authors: von Buren, G., Rodoni, L., Kromer, C., Jackel, H., Huber, A., Morf, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2006
• Subjects: Bandwidth; Bit error rate; Circuits; Clocks; CMOS technology; Laboratories; Latches; Master-slave; Phase detection; Sampling methods
• ISBN: 9781424403035; 1424403022; 9781424403028; 1424403030
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIR.2006.307542

A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10 -12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a snail area of 30times20 mum 2