Design of a 11 bit 10Ms/s pipelined A/D converter

A 11 bit 10Ms/s A/D Converter (ADC) is presented. The converter consists of a five-stage pipelined architecture and adopts the negative redundant digital correction technique to correct errors in the gain and offset. The fully differential circuitry is used to improve the power supply rejection and...

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Bibliographic Details

Published in:	ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) pp. 310 - 313
Main Authors:	Peng Bailin, Cheng Jun, Chen Guican
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2001
Subjects:	CMOS technology Differential amplifiers Digital systems Error correction Feedback circuits Power supplies Samarium Switches Switching circuits Voltage
Online Access:	Get full text
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