Application of lightly doped buried-layer for the reduction of the interconnection and junction capacitances

• Published in: Proceedings of the Bipolar Circuits and Technology Meeting pp. 198 - 201
• Main Authors: Iranmanesh, A., Jerome, R., Solheim, A., Ilderem, V., Dadgar, A., Bouknight, L., Biswal, M., Batani, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1989
• Subjects: Capacitance; Conducting materials; Delay; Dielectric constant; Dielectric materials; Dielectric substrates; Equations; Integrated circuit interconnections; Lead; MOSFETs
• DOI: 10.1109/BIPOL.1989.69491

Interconnection delay plays a dominant role in determining the speed performance of todays integrated circuits. It is shown that the formation of a lightly doped buried layer (LDBL) reduces the capacitance of wiring leads and bonding pads with respect to the substrate. LDBL also improves the collector-to-substrate capacitance of npn transistors as well as the tub-to-substrate capacitance of MOS transistors. As a result the speed performance of the products employing this technique is significantly improved. Because of the relative simplicity of the process, the ratio of percent delay reduction to percent cost increase is expected to be smaller than for any alternative approach.< >