3-layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator With High Density TSV For Advanced CMOS Image Sensor Applications

• Published in: 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 305 - 311
• Main Authors: Nicolas, Stephane, Suarez-Berru, Jerzy-Javier, Bresson, Nicolas, Socquet-Clerc, Carole, Assous, Myriam, Borel, Stephan, Velard, Remi, Dechamp, Jerome, Bouis, Renan, Roman, Antonio, Abadie, Karine, Hebras, Damien
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28-05-2024
• Subjects: 3D Integration; CMOS image sensors; Fabrication; Fine pitch; High Density TSV; Hybrid Bonding; Kelvin; Metals; Resistance; Test Vehicle; Three-dimensional displays; Wafer Level Packaging
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51529.2024.00057

After having successfully demonstrating a 2-layer face-to-back (F2B) test vehicle (TV), we reached the next level of integration by achieving a 3-layer TV with fine-pitch Cu-Cu hybrid bonding (HB) technology and high-density (HD) Through Silicon Via (TSV). Different Cu damascene levels that simulate back-end-of-line (BEOL) layers are used on 300mm wafers to fabricate the 3-layer TV. After having bonded the first two wafers (tier 1 and tier 2) within a face-to-face (F2F) hybrid bonding configuration, the backside of tier 2 is thinned down to 9 μm. 1x10μm TSVs are then fabricated to connect tier 2 to tier 3 via a face-to-back (F2B) hybrid bonding step. After the TV fabrication, we performed morphological characterizations (FIB-SEM cross-sections) to verify the entire 3D stacked structure. We reported advanced 3D cross-sections showing the good metal connection at the HB and TSV interfaces. For electrical characterization, different types of Kelvin and Daisy Chain (DC) structures (up to 6500 half links) are tested. Our test structures are designed with either standard or fine pitch configurations (Pitch: 6 μm and 4 μm respectively) with HB pad dimensions of 3x3 μm 2 and 2x2 μm 2 respectively. The results for the Kelvin structures show a median resistance of a few ohms with high yield (over 80%). These results are confirmed by electrical measurements on DC structures. After demonstrating 3-layer TV functionality, the next step will be to implement this 3D technology in a functional advanced CMOS image sensor (CIS) in the next coming years.