Design Methodology and Timing Considerations for implementing a TDC on a Cyclone V FPGA Target

• Published in: 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) pp. 126 - 129
• Main Authors: Khaddour, Wassim, Dadouche, Foudil, Uhring, Wilfried, Frick, Vincent, Madec, Morgan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2020
• Subjects: Adders; Carry Chain Logic; Clocks; Cyclones; Delays; Field programmable gate arrays; Field-Programmable Gate Array (FPGA); Registers; routing delay; Time-to-Digital Converter (TDC)
• DOI: 10.1109/NEWCAS49341.2020.9159812

There are hundreds of research publications that theoretically discuss the implementation of Tapped Delay Line based Time to Digital Converters (TDL TDCs) on Field-Programmable Gate Array (FPGA) targets. However, most of these works do not cover the timing issues that will be encountered mostly due to the routing delays. The purpose of this work is to highlight the main timing issues that should be considered when implementing TDCs in FPGA targets and propose practical approaches to overcome these issues. As a study case, a full design methodology of a TDC on a Cyclone V FPGA target is presented in this work.