1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation

This paper presents an outlook of Crossbar memory array capabilities while operated in the sub-threshold regime. By means of experimental data obtained on a RRAM resistive device co-integrated in series with an OTS back-end selector, the pertinence of 1S1R sub-threshold read operation for both stand...

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Bibliographic Details
Published in:	2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) pp. 1 - 6
Main Authors:	Lopez, Joel Minguet, Dampfhoffer, Manon, Hirtzlin, Tifenn, Reganaz, Lucas, Grenouillet, Laurent, Navarro, Gabriele, Bernard, Mathieu, Magis, Thomas, Carabasse, Catherine, Castellani, Niccolo, Meli, Valentina, Vianello, Elisa, Deleruyelle, Damien, Portal, Jean-Michel, Molas, Gabriel, Andrieu, Francois
Format:	Conference Proceeding
Language:	English
Published:	Lodz University of Technology 29-06-2023
Subjects:	1S1R BNN BSNN chalcogenide Computer architecture crossbar crosspoint Data models Energy efficiency Hardware inference Microprocessors Neural network hardware OTS PCM RRAM Training
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Summary:	This paper presents an outlook of Crossbar memory array capabilities while operated in the sub-threshold regime. By means of experimental data obtained on a RRAM resistive device co-integrated in series with an OTS back-end selector, the pertinence of 1S1R sub-threshold read operation for both standard Binarized Neural Networks (BNNs) and Binarized Spiking Neural Networks (B'SNNs) inference implementation in hardware is elucidated.
DOI:	10.23919/MIXDES58562.2023.10203226