Delay estimation and measurement circuit for a high-speed CMOS clocked comparator

• Published in: 2017 European Conference on Circuit Theory and Design (ECCTD) pp. 1 - 4
• Main Authors: Cron, L., Laugier, P., Ferreira, P. Maris, Vinci dos Santos, Filipe, Benabes, Philippe
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2017
• Subjects: Analytical models; Clocks; comparator; delay; Delays; double tail; Frequency measurement; Integrated circuit modeling; latch; Mathematical model; measurement circuit; Monte-Carlo Analysis; PVT; temperature; Temperature measurement
• ISSN: 2474-9672
• DOI: 10.1109/ECCTD.2017.8093261

Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a wide temperature range. The results given by this model agree well with spice postlayout simulation for a CMOS 0.18-μm SOI process, taking into consideration both process and temperature variations. To verify experimentally the correctness of the model we also propose a novel on-chip fully digital asynchronous architecture to measure the delay of the comparator, robust against extreme temperature variations.