LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching

• Published in: 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS) pp. 65 - 69
• Main Authors: BRITTON, Giovani, MIR, Salvador, LAUGA-LARROZE, Estelle, DORMIEU, Benjamin, LUGO, Jose, AZEVEDO, Joao, SADLO, Sebastien, BERLINGARD, Quentin, CASSE, Mickael, GALY, Philippe
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-06-2024
• Subjects: Capacitors; Cryo-CMOS; Cryogenics; Fano factor; LNA; Look-Up Table; Noise; Noise figure; Quantum computing; Qubit; Silicon; Table lookup
• ISSN: 2474-9672
• DOI: 10.1109/NewCAS58973.2024.10666334

In recent years, cryogenic silicon electronics have gained increased interest for applications in fields such as quantum computers and space exploration. Unfortunately, commercial technologies lack cryogenic compact models for circuit design. In this paper, we target the sizing of the critical input stage of a power efficient low-noise amplifier working at 7 GHz and 4 K with simultaneous noise and power matching for meeting the stringent specifications of a gate-dispersive readout circuit for spin quantum bits. In the absence of a compact model for the transistors in 28 nm FD-SOI technology, we propose a design methodology using a look-up table that has been buit with 4 K DC measurements of technology transistors and their associated capacitors to demonstrate the feasibility of the circuit.