Impact of process parameters on circuit performance for the 32 nm technology node

• Published in: Microelectronic engineering Vol. 84; no. 11; pp. 2738 - 2743
• Main Authors: Farcy, A., Gallitre, M., Arnal, V., Sellier, M., Guibe, L., Blampey, B., Bermond, C., Fléchet, B., Torres, J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Amsterdam Elsevier B.V 01-11-2007; Elsevier Science
• Subjects: 32 nm node; Applied sciences; Circuit optimization; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Interconnects; Propagation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Circuit optimization; 32 nm node; Propagation; Performance; Interconnects; Delay; Performance evaluation; Driver; Optimization; Time domain method; Interconnection; Integrated circuit; Delay time
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2007.05.015

As IC dimensions scale down to the 32
nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.