Simulation of Novel Nano Low-Dimensional FETs at the Scaling Limit

• Published in: Nanomaterials (Basel, Switzerland) Vol. 14; no. 17; p. 1375
• Main Authors: Guo, Pengwen, Zhou, Yuxue, Yang, Haolin, Pan, Jiong, Yin, Jiaju, Zhao, Bingchen, Liu, Shangjian, Peng, Jiali, Jia, Xinyuan, Jia, Mengmeng, Yang, Yi, Ren, Tianling
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 23-08-2024
• Subjects: 2D materials; CNT; Complexity; Electric fields; Electrons; Electrostatic properties; Fabrication; Field effect transistors; FinFET; GAAFET; Molybdenum disulfide; Multi wall carbon nanotubes; nanosheet FET; Nodes; Performance enhancement; Scaling; Silicon; Simulation; Single wall carbon nanotubes; sub-3 nm node; Transistors; Two dimensional materials; nanosheet FET; TCAD simulation; GAAFET; sub-3 nm node; 2D materials; FinFET; CNT
• ISSN: 2079-4991; 2079-4991
• DOI: 10.3390/nano14171375

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS
layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS
, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit.