A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

A submicron pixel's light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e /s at 60 °C, an ul...

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Bibliographic Details
Published in:	Sensors (Basel, Switzerland) Vol. 17; no. 12; p. 2816
Main Authors:	Takahashi, Seiji, Huang, Yi-Min, Sze, Jhy-Jyi, Wu, Tung-Ting, Guo, Fu-Sheng, Hsu, Wei-Cheng, Tseng, Tung-Hsiung, Liao, King, Kuo, Chin-Chia, Chen, Tzu-Hsiang, Chiang, Wei-Chieh, Chuang, Chun-Hao, Chou, Keng-Yu, Chung, Chi-Hsien, Chou, Kuo-Yu, Tseng, Chien-Hsien, Wang, Chuan-Joung, Yaung, Dun-Nien
Format:	Journal Article
Language:	English
Published:	Switzerland MDPI AG 05-12-2017 MDPI
Subjects:	CMOS Dark current Digital cameras full well capacity Image enhancement image sensor optical crosstalk Pixels random telegraph noise read noise stacked CMOS image sensor submicron pixel random telegraph noise read noise dark current full well capacity image sensor optical crosstalk submicron pixel stacked CMOS image sensor
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Summary:	A submicron pixel's light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e /s at 60 °C, an ultra-low read noise of 0.90 e ·rms, a high full well capacity (FWC) of 4100 e , and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.
Bibliography:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 This paper is an expanded version of our published paper: Takahashi, S.; Huang, Y.-M.; Sze, J.-J.; Wu, T.-T.; Guo, F.-S.; Hsu, W.-C.; Tseng, T-H.; Liao, K.; Kuo, C.-C.; Chen, T.-H.; et al. Low Dark Current and Low Noise 0.9 µm Pixel in a 45 nm Stacked CMOS Image Sensor Process Technology. In Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan, 30 May–2 June 2017.
ISSN:	1424-8220 1424-8220
DOI:	10.3390/s17122816