Metrology for the next generation of semiconductor devices

• Published in: Nature electronics Vol. 1; no. 10; pp. 532 - 547
• Main Authors: Orji, N. G., Badaroglu, M., Barnes, B. M., Beitia, C., Bunday, B. D., Celano, U., Kline, R. J., Neisser, M., Obeng, Y., Vladar, A. E.
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 2018
• Subjects: 639/166/987; 639/624/1107; 639/766/25; 639/925/927; 639/925/930; Electrical Engineering; Engineering; Review Article; AFM; SEM; Scatterometry; TEM; CD-SAX; nanometrology
• ISSN: 2520-1131; 2520-1131
• DOI: 10.1038/s41928-018-0150-9

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.
This Review Article examines state-of-the-art metrology methods for integrated circuits and highlights how new integrated circuit device design and industry requirements affect lithography options and consequently metrology requirements.