Design for manufacturability and reliability in extreme-scaling VLSI

• Published in: Science China. Information sciences Vol. 59; no. 6; pp. 92 - 114
• Main Authors: Yu, Bei, Xu, Xiaoqing, Roy, Subhendu, Lin, Yibo, Ou, Jiaojiao, Pan, David Z.
• Format: Journal Article
• Language: English
• Published: Beijing Science China Press 01-06-2016; Springer Nature B.V
• Subjects: Circuit design; Computer Science; Design for manufacturability; Design optimization; Information Systems and Communication Service; Integrated circuits; R&D; Reliability; Research & development; Review; Transistors; Very large scale integration; 半导体行业; 可制造性; 可靠性设计; 可靠性问题; 特征尺寸; 超大规模集成电路; 长期规划; 集成电路设计; design for manufacturability; design for reliability; VLSI CAD
• ISSN: 1674-733X; 1869-1919
• DOI: 10.1007/s11432-016-5560-6

In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore＇s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14 nm nanometer regime, modern integrated circuit（IC） designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.