A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

• Published in: IEEE journal of solid-state circuits Vol. 43; no. 2; pp. 518 - 529
• Main Authors: Tae-Hyoung Kim, Liu, J., Keane, J., Kim, C.H.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-02-2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Channels; Circuit properties; CMOS logic circuits; CMOS process; Decoders; Decoding; Delay; Design. Technologies. Operation analysis. Testing; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Grounds; Integrated circuits; Integrated circuits by function (including memories and processors); Logic; Logic circuits; Low-voltage memory; MOSFETs; Random access memory; reverse short channel effect; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Sizing; Static random access memory; subthreshold SRAM; Voltage; voltage scaling; Performance evaluation; Static random access memory; subthreshold SRAM; Random access memory; Short channel; Decoding circuit; Low-voltage memory; Dimensioning; Low voltage; Complementary MOS technology; Integrated circuit; voltage scaling; Delay time; reverse short channel effect
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.914328

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.