Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

• Published in: IEEE transactions on electron devices Vol. 55; no. 1; pp. 48 - 59
• Main Authors: Akarvardar, K., Eggimann, C., Tsamados, D., Singh Chauhan, Y., Wan, G.C., Ionescu, A.M., Howe, R.T., Wong, H.-S.P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Devices; Electric potential; Electrostatic actuators; FETs; Force; Gates (circuits); Integrated circuit modeling; inverter; Logic; Logic circuits; Logic gates; Mathematical analysis; Mathematical models; microelectromechanical system (MEMS); MOSFET; MOSFET circuits; MOSFETs; nanoelectromechanical field-effect transistor (NEMFET); nanoelectromechanical systems (NEMS); resonant-gate FET; subthreshold swing; suspended-gate FET (SGFET); Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2007.911070

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.