Effects of process variation in VLSI interconnects - a technical review

• Published in: Microelectronics international Vol. 26; no. 3; pp. 49 - 55
• Main Authors: Verma, K.G, Kaushik, B.K, Singh, R
• Format: Journal Article
• Language: English
• Published: Bradford Emerald Group Publishing Limited 31-07-2009; MCB University Press
• Subjects: Applied sciences; Custom design; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Geometry; Integrated circuit technology; Integrated circuits; Interconnect; Metal oxides; Operations and production management; Operations management; Radiation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Studies; Transistors; Integrated circuit technology; Operations and production management; Production management; VLSI circuit; Interconnection; Crosstalk; Integrated circuit; Response surface; Delay time; Review; Stochastic process; Deterministic approach
• ISSN: 1356-5362; 1758-812X
• DOI: 10.1108/13565360910981562

Purpose - Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design methodology approach - The impacts of these interconnect process variations on circuit delay and cross-talk noises along with the two major sources of delays - parametric delay variations and global interconnect delays - have been discussed.Findings - Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non-deterministic.Originality value - This paper usefully reviews process variation effects on very large-scale integration (VLSI) interconnect.