Memory allocation and mapping in high-level synthesis - an integrated approach

With the increasing design complexity and performance requirement, data arrays in behavioral specification are usually mapped to memories in behavioral synthesis. This paper describes a new algorithm that overcomes two limitations of the previous works on the problem of memory-allocation and array-m...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 11; no. 5; pp. 928 - 938
Main Authors: Jaewon Seo, Taewhan Kim, Panda, P.R.
Format: Journal Article
Language:English
Published: Piscataway, NJ IEEE 01-10-2003
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:With the increasing design complexity and performance requirement, data arrays in behavioral specification are usually mapped to memories in behavioral synthesis. This paper describes a new algorithm that overcomes two limitations of the previous works on the problem of memory-allocation and array-mapping to memories. Specifically, its key features are a tight link to the scheduling effect, which was totally or partially ignored by the existing memory synthesis systems, and supporting nonuniform access speeds among the ports of memories, which greatly diversify the possible (practical) memory configurations. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding globally best memory configurations.
Bibliography:ObjectType-Article-2
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2003.817116