Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for g...

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Published in:IEEE transactions on electron devices Vol. 52; no. 3; pp. 352 - 359
Main Authors: Noguchi, J., Sato, K., Konishi, N., Uno, S., Oshima, T., Ishikawa, K., Ashihara, H., Saito, T., Kubo, M., Tamaru, T., Yamada, Y., Aoki, H., Fujiwara, T.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01-03-2005
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Abstract A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.
AbstractList A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.
Author Sato, K.
Ishikawa, K.
Yamada, Y.
Tamaru, T.
Kubo, M.
Uno, S.
Aoki, H.
Konishi, N.
Saito, T.
Noguchi, J.
Fujiwara, T.
Oshima, T.
Ashihara, H.
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Cites_doi 10.1109/IITC.2000.854347
10.1109/VLSIT.1996.507801
10.1109/IEDM.2003.1269337
10.1109/RELPHY.2003.1197759
10.1109/IITC.2001.930003
10.1109/IITC.1998.704769
10.1016/S0167-9317(03)00438-6
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Issue 3
Keywords stress
Electric breakdown
Dry process
Metallizing
IC interconnections
Air-gaps
Damascene process
Self aligned technology
Time dependence
Microelectronic fabrication
Effective dielectric constant
Interconnection
Complementary MOS technology
seals
Integrated circuit
Air gap
Capacitance
copper
Leakage current
Miniaturization
Reliability
Sacrificial layer
Damaging
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References aoki (ref10) 2001
kinoshita (ref12) 2000
ref11
arnal (ref5) 2001
ref1
noguchi (ref8) 2003
ogawa (ref2) 2003
noguchi (ref13) 2001
ref7
ref9
ref4
ref3
ref6
References_xml – start-page: 166
  year: 2003
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– ident: ref6
  doi: 10.1016/S0167-9317(03)00438-6
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StartPage 352
SubjectTerms Air-gaps
Applied sciences
capacitance
CMOS integrated circuits
Copper
Design. Technologies. Operation analysis. Testing
Electric breakdown
Electronics
Etching
Exact sciences and technology
IC interconnections
Integrated circuit interconnections
Integrated circuit metallization
Integrated circuit reliability
Integrated circuits
Leakage currents
Microelectronic fabrication (materials and surfaces technology)
reliability
seals
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
stress
Title Process and reliability of air-gap Cu interconnect using 90-nm node technology
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Volume 52
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