Process and reliability of air-gap Cu interconnect using 90-nm node technology
A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for g...
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Published in: | IEEE transactions on electron devices Vol. 52; no. 3; pp. 352 - 359 |
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Main Authors: | , , , , , , , , , , , , |
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01-03-2005
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Abstract | A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant. |
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AbstractList | A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant. |
Author | Sato, K. Ishikawa, K. Yamada, Y. Tamaru, T. Kubo, M. Uno, S. Aoki, H. Konishi, N. Saito, T. Noguchi, J. Fujiwara, T. Oshima, T. Ashihara, H. |
Author_xml | – sequence: 1 givenname: J. surname: Noguchi fullname: Noguchi, J. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 2 givenname: K. surname: Sato fullname: Sato, K. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 3 givenname: N. surname: Konishi fullname: Konishi, N. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 4 givenname: S. surname: Uno fullname: Uno, S. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 5 givenname: T. surname: Oshima fullname: Oshima, T. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 6 givenname: K. surname: Ishikawa fullname: Ishikawa, K. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 7 givenname: H. surname: Ashihara fullname: Ashihara, H. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 8 givenname: T. surname: Saito fullname: Saito, T. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 9 givenname: M. surname: Kubo fullname: Kubo, M. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 10 givenname: T. surname: Tamaru fullname: Tamaru, T. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 11 givenname: Y. surname: Yamada fullname: Yamada, Y. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 12 givenname: H. surname: Aoki fullname: Aoki, H. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan – sequence: 13 givenname: T. surname: Fujiwara fullname: Fujiwara, T. organization: Micro Device Div., Hitachi Ltd., Tokyo, Japan |
BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16555383$$DView record in Pascal Francis |
BookMark | eNqNkb1rHDEQxUVwIGcndYo0IpB0e9b3astwdj7AJCmcWsxKsxeZPeki7Rb330fmDIZUqYZhfu_Bm3dJLlJOSMhbzracs-H6_vZmKxjTW6ukteYF2XCt-24wylyQDWPcdoO08hW5rPWhrUYpsSHff5bssVYKKdCCc4QxznE50TxRiKXbw5HuVhrTgsXnlNAvdK0x7enAunSgKQekC_rfKc95f3pNXk4wV3zzNK_Ir8-397uv3d2PL992n-46r5RZOjlpKZge-TQqIULgAYIfQQnOpIch8BGkgSlwjQIR-x6NDZwJ8OMkBDB5RT6efY8l_1mxLu4Qq8d5hoR5rU5YLrVQ_wMyLdtvGvj-H_AhryW1EM6aXjMxaN2g6zPkS6614OSOJR6gnBxn7rEF11pwjy24cwtN8eHJFqqHeSqQfKzPMqObrZWNe3fmYsv7fJZDPzSnv-r8kTY |
CODEN | IETDAI |
CitedBy_id | crossref_primary_10_1039_c1jm11493j crossref_primary_10_1143_JJAP_50_016503 crossref_primary_10_1109_TSM_2008_2005396 crossref_primary_10_7567_JJAP_50_016503 crossref_primary_10_3390_electronics11182914 crossref_primary_10_1557_PROC_0914_F10_01 crossref_primary_10_1557_opl_2014_609 crossref_primary_10_1016_j_mee_2013_12_004 crossref_primary_10_1088_2515_7639_ad367b crossref_primary_10_1016_j_mee_2011_03_006 crossref_primary_10_1109_TED_2013_2244895 crossref_primary_10_1088_2515_7639_ad4c06 crossref_primary_10_1016_j_microrel_2016_01_015 crossref_primary_10_1063_1_4961877 crossref_primary_10_1109_TDMR_2004_831990 crossref_primary_10_1007_s12206_013_0981_2 crossref_primary_10_1143_JJAP_51_031501 crossref_primary_10_7567_JJAP_51_031501 crossref_primary_10_1016_j_mee_2016_02_019 crossref_primary_10_1143_JJAP_46_7678 crossref_primary_10_1016_j_mee_2008_05_020 crossref_primary_10_1109_TCPMT_2013_2265211 |
Cites_doi | 10.1109/IITC.2000.854347 10.1109/VLSIT.1996.507801 10.1109/IEDM.2003.1269337 10.1109/RELPHY.2003.1197759 10.1109/IITC.2001.930003 10.1109/IITC.1998.704769 10.1016/S0167-9317(03)00438-6 |
ContentType | Journal Article |
Copyright | 2005 INIST-CNRS Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005 |
Copyright_xml | – notice: 2005 INIST-CNRS – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005 |
DBID | 97E RIA RIE IQODW AAYXX CITATION 7SP 8FD L7M 8BQ JG9 |
DOI | 10.1109/TED.2005.843886 |
DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library Online Pascal-Francis CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace METADEX Materials Research Database |
DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts Materials Research Database METADEX |
DatabaseTitleList | Materials Research Database Technology Research Database |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library Online url: http://ieeexplore.ieee.org/Xplore/DynWel.jsp sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering Applied Sciences |
EISSN | 1557-9646 |
EndPage | 359 |
ExternalDocumentID | 2351750041 10_1109_TED_2005_843886 16555383 1397984 |
Genre | orig-research |
GroupedDBID | -~X .DC 0R~ 29I 3EH 4.4 5GY 5VS 6IK 97E AAJGR AASAJ ABQJQ ABVLG ACGFO ACGFS ACIWK ACKIV ACNCT AENEX AETIX AI. AIBXA AKJIK ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV B-7 BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD F5P HZ~ H~9 IAAWW IBMZZ ICLAB IDIHD IFIPE IFJZH IPLJI JAVBF LAI M43 MS~ O9- OCL P2P RIA RIE RIG RNS TAE TN5 VH1 VJK VOH XFK 08R ABPTK IQODW AAYXX CITATION 7SP 8FD L7M 8BQ JG9 |
ID | FETCH-LOGICAL-c446t-3f53205b1fb422dd1dadcba42103ca9d1ba36afd15e2eee77e68d102acbf22a03 |
IEDL.DBID | RIE |
ISSN | 0018-9383 |
IngestDate | Fri Aug 16 21:24:30 EDT 2024 Fri Aug 16 04:46:03 EDT 2024 Thu Oct 10 18:15:31 EDT 2024 Fri Aug 23 01:23:34 EDT 2024 Sun Oct 22 16:07:13 EDT 2023 Wed Jun 26 19:20:33 EDT 2024 |
IsPeerReviewed | true |
IsScholarly | true |
Issue | 3 |
Keywords | stress Electric breakdown Dry process Metallizing IC interconnections Air-gaps Damascene process Self aligned technology Time dependence Microelectronic fabrication Effective dielectric constant Interconnection Complementary MOS technology seals Integrated circuit Air gap Capacitance copper Leakage current Miniaturization Reliability Sacrificial layer Damaging |
Language | English |
License | CC BY 4.0 |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-c446t-3f53205b1fb422dd1dadcba42103ca9d1ba36afd15e2eee77e68d102acbf22a03 |
Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
PQID | 867502955 |
PQPubID | 23500 |
PageCount | 8 |
ParticipantIDs | crossref_primary_10_1109_TED_2005_843886 pascalfrancis_primary_16555383 proquest_journals_867502955 proquest_miscellaneous_28135240 proquest_miscellaneous_28053018 ieee_primary_1397984 |
PublicationCentury | 2000 |
PublicationDate | 2005-03-01 |
PublicationDateYYYYMMDD | 2005-03-01 |
PublicationDate_xml | – month: 03 year: 2005 text: 2005-03-01 day: 01 |
PublicationDecade | 2000 |
PublicationPlace | New York, NY |
PublicationPlace_xml | – name: New York, NY – name: New York |
PublicationTitle | IEEE transactions on electron devices |
PublicationTitleAbbrev | TED |
PublicationYear | 2005 |
Publisher | IEEE Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
References | aoki (ref10) 2001 kinoshita (ref12) 2000 ref11 arnal (ref5) 2001 ref1 noguchi (ref8) 2003 ogawa (ref2) 2003 noguchi (ref13) 2001 ref7 ref9 ref4 ref3 ref6 |
References_xml | – start-page: 166 year: 2003 ident: ref2 article-title: leakage, breakdown, and tddb characteristics of porous low-$\kappa$ silica-based interconnect dielectrics publication-title: Proc IRPS contributor: fullname: ogawa – ident: ref4 doi: 10.1109/IITC.2000.854347 – ident: ref7 doi: 10.1109/VLSIT.1996.507801 – ident: ref11 doi: 10.1109/IEDM.2003.1269337 – start-page: 68 year: 2003 ident: ref8 article-title: simple self-aligned air-gap interconnect process with cu/fsg structure publication-title: Proc IITC contributor: fullname: noguchi – start-page: 76 year: 2001 ident: ref10 article-title: robust 130 nm-node cu dual damascene technology with low-$\kappa$ barrier sicn publication-title: IEDM Tech Dig contributor: fullname: aoki – ident: ref1 doi: 10.1109/RELPHY.2003.1197759 – start-page: 298 year: 2001 ident: ref5 article-title: integration of a 3 level ${\rm cu{-}sio}_{2}$ air gap interconnect for sub 0.1 micron cmos technologies publication-title: Proc IITC contributor: fullname: arnal – start-page: 257 year: 2000 ident: ref12 article-title: process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-$\kappa$ organic film publication-title: IEDM Tech Dig contributor: fullname: kinoshita – ident: ref9 doi: 10.1109/IITC.2001.930003 – ident: ref3 doi: 10.1109/IITC.1998.704769 – start-page: 355 year: 2001 ident: ref13 article-title: impact of low-$\kappa$ dielectrics and barrier metals on tddb lifetime of cu interconnects publication-title: Proc IRPS contributor: fullname: noguchi – ident: ref6 doi: 10.1016/S0167-9317(03)00438-6 |
SSID | ssj0016442 |
Score | 1.9467819 |
Snippet | A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the... |
SourceID | proquest crossref pascalfrancis ieee |
SourceType | Aggregation Database Index Database Publisher |
StartPage | 352 |
SubjectTerms | Air-gaps Applied sciences capacitance CMOS integrated circuits Copper Design. Technologies. Operation analysis. Testing Electric breakdown Electronics Etching Exact sciences and technology IC interconnections Integrated circuit interconnections Integrated circuit metallization Integrated circuit reliability Integrated circuits Leakage currents Microelectronic fabrication (materials and surfaces technology) reliability seals Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices stress |
Title | Process and reliability of air-gap Cu interconnect using 90-nm node technology |
URI | https://ieeexplore.ieee.org/document/1397984 https://www.proquest.com/docview/867502955 https://search.proquest.com/docview/28053018 https://search.proquest.com/docview/28135240 |
Volume | 52 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV29T90wED_1MZWhQGnVAAUPDAxNib8Se0R8iImFIrFF_kRIkKD3Xob-9z3H4QFqhdQpluzBubPP97Pvfgdw6HnFopMIUxutS-E8LZWXdRk4Zw5BbjAh5TtfXjdXt-rsPNHk_FjlwoQQxuCz8DM1x7d837shXZUdJ29FKzGDGX5yrtbqxQDP9cwMTnEDI-yaaHxopY_RBOTLEyW4SknTr06gsaRKCog0C5RJzMUs_rLL42FzsfF_09yET5NTSU7yKtiCD6H7DOuvqAa34WrKCCCm82QeHu4zP_dv0kdi7uflnXkipwNJ7BFzl4Jf3JKkmPg7oquyeyRd7wNZru7hv8DNxfmv08tyqqVQOgR8y5LHVAFCWhqtYMx76o131ghEfNwZ7ak1vDbRUxkY_lDThFp5dD6Ms5ExU_GvsNb1XfgGhDZGRMGtMFwKa7VyNbepYFlyLiJrCjh6lm_7lCkz2hFqVLpFVaTCl7LNqihgO4nvZViWXAH7b_Tx0l9LiRaaF7D7rKB22nOLViH2qZiWsoCDVS9ulvQCYrrQD4uWKbQ5uELeG0HRJRXVzr9ntgsfR-7WMQhtD9aW8yF8h9nCD_vjcvwDMHzd7w |
link.rule.ids | 315,782,786,798,27933,27934,54767 |
linkProvider | IEEE |
linkToHtml | http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1Lb9QwEB7RcgAOvAoiFFofOHAgNH4l9hH1oa1a9kKRuEV-VpVKUu1uDv33HcfptgiE1Fsk--DMjMfz2TPfAHzyvGLRSYSpjdalcJ6Wysu6DJwzhyA3mJDqnWc_mvkvdXCYaHK-rGthQghj8ln4mj7Ht3zfuyFdle2laEUrsQGPpWjqJldrrd8M8GTP3OAUtzACr4nIh1Z6D51Avj5RgqtUNn3vDBqbqqSUSLNEqcTczuIvzzweN0cvHrbQl_B8CivJt2wHr-BR6F7Ds3tkg1swn2oCiOk8WYTLi8zQfU36SMzFojw3V2R_IIk_YuFS-otbkZQVf050VXa_Sdf7QFbrm_g38PPo8Gx_Vk7dFEqHkG9V8ph6QEhLoxWMeU-98c4agZiPO6M9tYbXJnoqA8MfappQK4_hh3E2MmYq_hY2u74L74DQxogouBWGS2GtVq7mNrUsS-FFZE0Bn2_l215l0ox2BBuVblEVqfWlbLMqCthK4rubliVXwM4f-rgbr6VEH80L2L5VUDvtumWrEP1UTEtZwO56FLdLegMxXeiHZcsUeh20kP_NoBiUiur9v1e2C09mZ99P29Pj-ck2PB2ZXMeUtA-wuVoM4SNsLP2wM5rmDQHX4UA |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Process+and+reliability+of+air-gap+Cu+interconnect+using+90-nm+node+technology&rft.jtitle=IEEE+transactions+on+electron+devices&rft.au=Noguchi%2C+J.&rft.au=Sato%2C+K.&rft.au=Konishi%2C+N.&rft.au=Uno%2C+S.&rft.date=2005-03-01&rft.pub=IEEE&rft.issn=0018-9383&rft.eissn=1557-9646&rft.volume=52&rft.issue=3&rft.spage=352&rft.epage=359&rft_id=info:doi/10.1109%2FTED.2005.843886&rft.externalDocID=1397984 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0018-9383&client=summon |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0018-9383&client=summon |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0018-9383&client=summon |