Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for g...

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Bibliographic Details
Published in:IEEE transactions on electron devices Vol. 52; no. 3; pp. 352 - 359
Main Authors: Noguchi, J., Sato, K., Konishi, N., Uno, S., Oshima, T., Ishikawa, K., Ashihara, H., Saito, T., Kubo, M., Tamaru, T., Yamada, Y., Aoki, H., Fujiwara, T.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01-03-2005
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.
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ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2005.843886