A pipeline architecture for computing the Euler number of a binary image

• Published in: Journal of systems architecture Vol. 51; no. 8; pp. 470 - 487
• Main Authors: Bishnu, Arijit, Bhattacharya, Bhargab B., Kundu, Malay K., Murthy, C.A., Acharya, Tinku
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01-08-2005; Elsevier Sequoia S.A
• Subjects: Algorithms; Euler number; Eulers equations; Image processing; Image processing systems; Pipeline architecture; Studies; VLSI; VLSI implementation; Pipeline architecture; Euler number; Image processing; VLSI implementation
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/j.sysarc.2004.12.001

Euler number of a binary image is a fundamental topological feature that remains invariant under translation, rotation, scaling, and rubber-sheet transformation of the image. In this work, a run-based method for computing Euler number is formulated and a new hardware implementation is described. Analysis of time complexity and performance measure is provided to demonstrate the efficiency of the method. The sequential version of the proposed algorithm requires significantly fewer number of pixel accesses compared to the existing methods and tools based on bit-quad counting or quad-tree, both for the worst case and the average case. A pipelined architecture is designed with a single adder tree to implement the algorithm on-chip by exploiting its inherent parallelism. The architecture uses O(
N) 2-input gates and requires O(
N
log
N) time to compute the Euler number of an
N
×
N image. The same hardware, with minor modification, can be used to handle arbitrarily large pixel matrices. A standard cell based VLSI implementation of the architecture is also reported. As Euler number is a widely used parameter, the proposed design can be readily used to save computation time in many image processing applications.