Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

• Published in: IEEE electron device letters Vol. 22; no. 5; pp. 227 - 229
• Main Authors: Yee-Chia Yeo, Qiang Lu, Ranade, P., Takeuchi, H., Yang, K.J., Polishchuk, I., Tsu-Jae King, Chenming Hu, Song, S.C., Luan, H.F., Dim-Lee Kwong
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance-voltage characteristics; Chemical vapor deposition; CMOS technology; Dielectrics; Electrodes; FETs; Field effect transistors; Gates; Mathematical models; MOSFET circuits; Oxides; Predictive models; Semiconductors; Silicon; Silicon nitride; Titanium
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.919237

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.