A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 5; pp. 769 - 773
• Main Authors: Durlam, M., Naji, P.J., Omair, A., DeHerrera, M., Calder, J., Slaughter, J.M., Engel, B.N., Rizzo, N.D., Grynkewich, G., Butcher, B., Tracy, C., Smith, K., Kyler, K.W., Ren, J.J., Molla, J.A., Feil, W.A., Williams, R.G., Tehrani, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Access time; Circuits; CMOS; CMOS memory circuits; CMOS technology; CONNECTORS (ELECTRICAL); Copper; ELECTRICAL CONDUCTIVITY; FLUXES; Integrated circuit interconnections; Integrated circuit technology; Magnetic circuits; Magnetic flux; Magnetic tunneling; Magnetoresistive random access memory; MAGNETORESISTIVITY; Programming; Random access memory; Tunnel junctions; Tunneling magnetoresistance
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.810048

A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm/sup 2/ 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-/spl mu/m CMOS process utilizing five layers of metal and two layers of poly.