Accelerated quantum Monte Carlo with probabilistic computers

• Published in: Communications physics Vol. 6; no. 1; pp. 85 - 9
• Main Authors: Chowdhury, Shuvro, Camsari, Kerem Y., Datta, Supriyo
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 27-04-2023; Nature Publishing Group; Nature Portfolio
• Subjects: 639/705/1042; 639/766/483/3926; 639/925/927; Algorithms; Annealing; Central processing units; Computer engineering; Computer simulation; Computers; CPUs; Hardware; Ising model; Microprocessors; Phase transitions; Physics; Physics and Astronomy; Quantum computing; Qubits (quantum computing)
• ISSN: 2399-3650; 2399-3650
• DOI: 10.1038/s42005-023-01202-3

Quantum Monte Carlo (QMC) techniques are widely used in a variety of scientific problems and much work has been dedicated to developing optimized algorithms that can accelerate QMC on standard processors (CPU). With the advent of various special purpose devices and domain specific hardware, it has become increasingly important to establish clear benchmarks of what improvements these technologies offer compared to existing technologies. In this paper, we demonstrate 2 to 3 orders of magnitude acceleration of a standard QMC algorithm using a specially designed digital processor, and a further 2 to 3 orders of magnitude by mapping it to a clockless analog processor. Our demonstration provides a roadmap for 5 to 6 orders of magnitude acceleration for a transverse field Ising model (TFIM) and could possibly be extended to other QMC models as well. The clockless analog hardware can be viewed as the classical counterpart of the quantum annealer and provides performance within a factor of < 10 of the latter. The convergence time for the clockless analog hardware scales with the number of qubits as ∼ 
N
, improving the ∼ 
N
2
scaling for CPU implementations, but appears worse than that reported for quantum annealers by D-Wave.
Quantum Monte Carlo (QMC) techniques have been very successful in quantum simulation. This paper shows a pathway to provide orders of magnitude speedup to QMC simulations through massively parallel architectures (both digital and mixed signal) while maintaining a scaling advantage over QMC implemented in software.