Thermal design optimization of electronic circuit board layout with transient heating chips by using Bayesian optimization and thermal network model

• Published in: International journal of heat and mass transfer Vol. 184; p. 122263
• Main Authors: Otaki, Daiki, Nonaka, Hirofumi, Yamada, Noboru
• Format: Journal Article
• Language: English
• Published: Oxford Elsevier Ltd 01-03-2022; Elsevier BV
• Subjects: Artificial intelligence; Bayesian analysis; Bayesian optimization; Capacitance; Circuit design; Circuits; Design optimization; Electrical circuit board; Electronic circuits; Electronic devices; Gaussian process; Genetic algorithms; Layouts; Performance enhancement; Printed circuit boards; Swarm intelligence; Thermal design; Thermal energy; Thermal network model; Transient heating; Thermal network model; Bayesian optimization; Electrical circuit board; Artificial intelligence; Thermal design
• ISSN: 0017-9310; 1879-2189
• DOI: 10.1016/j.ijheatmasstransfer.2021.122263

•Bayesian optimization used with a lumped-capacitance thermal network model.•Layout of the unsteady heating chips on the electronic circuit board is optimized.•Bayesian optimization is faster than other algorithms by a factor of 4,5.•Bayesian optimization quickly finds optimal layouts from 10 million layout patterns.
This paper describes a method combining Bayesian optimization (BO) and a lumped-capacitance thermal network model that is effective for speeding up the thermal design optimization of an electronic circuit board layout with transient heating chips. As electronic devices have become smaller and more complex, the importance of thermal design optimization to ensure heat dissipation performance has increased. However, such a thermal design optimization is difficult because various trade-offs associated with packaging and transient temperature changes of heat-generating components must be considered. This study aims to improve the performance of thermal design optimization by artificial intelligence. BO using a Gaussian process was combined with the lumped-capacitance thermal network model, and its performance was verified. As a result, BO successfully found the ideal circuit board layout as well as particle swarm optimization (PSO) and genetic algorithm (GA) could. The CPU time for BO was 1/5 and 1/4 of that for PSO and GA. In addition, BO found a non-intuitive optimal solution in approximately 7 min from 10 million layout patterns. It was estimated that this was 1/1000 of the CPU time required for analyzing all layout patterns.