Experimental Characterization and Simulation of Electron-Induced SEU in 45-nm CMOS Technology

• Published in: IEEE transactions on nuclear science Vol. 61; no. 6; pp. 3055 - 3060
• Main Authors: Samaras, A., Pourrouquet, P., Sukhaseum, N., Gouyet, L., Vandevelde, B., Chatry, N., Ecoffet, R., Bezerra, F., Lorfevre, E.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 45-nm FPGA; CMOS technology; embedded RAM; Field programmable gate arrays; high-energy electron; Monte Carlo methods; Monte Carlo simulation; Performance evaluation; Radiation effects; radiation test; Random access memory; SEU rate; Single event upsets; single-event upset
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2014.2367544

This paper presents the single-event upset characterization of a commercial field programmable gate array (FPGA) using electron radiation. FPGA radiation test results under high energy electrons are described and the dependence between electron energy and SEU cross section is highlighted. A technological cross section is performed to evaluate the back end of line (BEOL) layers composition and thickness. These values are used to perform Monte Carlo simulations of the commercial FPGA exposed to 20-MeV primary electron beam. Calculation results show that electrons are able to generate SEU on the FPGA embedded RAM and confirmed experimental data. SEU rates induced by Jovian electrons are estimated using two different tools: Monte Carlo in GEANT4 and the OMERE Software.