Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 10; no. 6; pp. 856 - 863
• Main Authors: Givargis, T., Vahid, F., Henkel, J.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01-12-2002; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Application software; Applied sciences; Computational modeling; Computer science; Computer simulation; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Integrated circuits; Mathematical models; Microprocessors; National electric code; Object oriented; Object oriented modeling; Object-oriented programming; Power system modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System on chip; System-on-a-chip; Very large scale integration; Trace analysis; Energy consumption; Parameter estimation; Cache memory; System on a chip; power estimation; Experimental study; Modeling; Implementation; Computation time; Experimental result; Power consumption; Integrated circuit; System simulation; system- level simulation; Memory circuit; Microprocessor; Low-power electronics; Low-power design; system-on-a-chip design; Object oriented programming; Computer aided design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2002.808443

Various core-based power evaluation approaches for microprocessors, caches, memories and buses have been proposed in the past. We propose a new power evaluation technique that is targeted toward peripheral cores. Our approach is the first to combine for peripherals both gate-level-obtained power data with a system-level simulation model written in an object-oriented language. Our approach decomposes peripheral functionality into so-called instructions. The approach can be applied with three increasingly fast methods: system simulation, trace simulation or trace analysis. We show that our models are sufficiently accurate in order to make power-related system-level design decisions but at a computation time that is orders of magnitude faster than a gate-level simulation.