A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 5; pp. 1038 - 1046
• Main Authors: Grace, C.R., Hurst, P.J., Lewis, S.H.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-05-2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive systems; Algorithms; Amplification; Amplifiers; Analog-digital conversion; analog-to-digital conversion; Applied sciences; bootstrapped calibration; Calibration; Circuit properties; CMOS analog integrated circuits; CMOS technology; Design. Technologies. Operation analysis. Testing; digital background calibration; Digital-analog conversion; Dynamic range; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Gain; Integrated circuits; Integrated circuits by function (including memories and processors); Linearity; Microprocessors; Nonlinearity; Prototypes; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal processing algorithms; Signal to noise ratio; Studies; Testing; Adaptive systems; Prototype; CMOS analog integrated circuits; Adaptive system; Non linear phenomenon; AD converter; Complementary MOS technology; CMOS analogue integrated circuits; Queue; bootstrapped calibration; Closed loop; Spurious free dynamic range; DA converter; Amplifier; digital background calibration; Algorithm; Pipeline processing; Boarded computer; analog-to-digital conversion; Queueing system; Integrated circuit; Slew rate; Accommodation; Microprocessor; Gain; Signal to noise and distortion ratio
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.845972

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.