Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 6; pp. 639 - 649
• Main Authors: Chakraborty, A., Duraisami, K., Sathanur, A., Sithambaram, P., Benini, L., Macii, A., Macii, E., Poncino, M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NJ IEEE 01-06-2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Buffer storage; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clock skew; clock tree design; Clocks; Delay; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy management; Exact sciences and technology; Integrated circuit interconnections; Power dissipation; Studies; temperature; Temperature distribution; Temperature sensors; thermal design; Thermal management; Tunable circuits and devices; Temperature distribution; Tunable circuit; High performance; Thermal behavior; System design; Clock; thermal design; Algorithm; Clock skew; Spatial distribution; Thermal compensation; temperature; clock tree design; Delay time; Delay line
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2000248

The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, redesign of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this paper, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed offline and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with worst-case power and area penalty of 3.5% and 5.5% respectively.