A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 4; pp. 1298 - 1305
• Main Authors: Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-04-2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Applied sciences; Bandwidth; Channels; Circuit properties; Circuits; CMOS; CMOS technology; Core loss; Crosstalk; Current integration; decision feedback equalizer; Decision feedback equalizers; Design. Technologies. Operation analysis. Testing; Dielectric losses; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equalizers; Exact sciences and technology; Feedback; Integrated circuits; Intersymbol interference; Noise levels; Nonlinear distortion; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; serial link; Serials; SOI; Summer; Timing; Serial transmission; Frequency dependence; Feedback regulation; Receiver; Rail to rail characteristics; Decision feedback equalizers; SOI; decision feedback equalizer; serial link; Silicon on insulator technology; Complementary MOS technology; Summing circuits; Current integration; Sampling; Low-power electronics; Ecological approach; Design for environment
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2014733

The design and experimental results of a low-power, low-area 5-tap decision feedback equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported. The DFE employs a low-power current-integrating summer with sampling front-end, which eliminates systematic frequency-dependent loss inherent in conventional integrating serial receivers. Further power and area savings are achieved through the use of a direct-feedback architecture and CMOS-style rail-to-rail clocking. The 5-tap DFE core occupies 73 times 50 mum 2 and consumes 11 mW from a 1 V supply when equalizing 12 Gb/s data passed over a 30" channel with 15 dB of loss at 6 GHz.