A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power chara...
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Published in: | IEEE journal of solid-state circuits Vol. 42; no. 10; pp. 2161 - 2168 |
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Main Authors: | , |
Format: | Journal Article Conference Proceeding |
Language: | English |
Published: |
New York, NY
IEEE
01-10-2007
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects: | |
Online Access: | Get full text |
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