A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 10; pp. 2161 - 2168
• Main Authors: HONG, Hao-Chiao, LEE, Guo-Ming
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-10-2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ADC; Analog circuits; Applied sciences; Approximation; Bandwidth; Circuit properties; Circuit synthesis; CMOS; Costs; Design. Technologies. Operation analysis. Testing; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy efficiency; energy efficient; Energy resolution; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); low power; low supply voltage; Low voltage; Mathematical analysis; MOSFETs; mu W design; Noise levels; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal to noise ratio; successive approximation; Switches; Switching, multiplexing, switched capacity circuits; Threshold voltage; Voltage; ADC; μW design; 8 bit Processor; Rail to rail characteristics; Bootstrap circuits; Low voltage; Successive approximation; Energy characteristic; Power consumption; AD converter; Complementary MOS technology; low power; low supply voltage; Selector switch; energy efficient; Low-power electronics; Figure of merit; Signal to noise and distortion ratio
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.905237

An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step.