The Data Vortex Optical Packet Switched Interconnection Network

A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An...

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Bibliographic Details
Published in:Journal of lightwave technology Vol. 26; no. 13; pp. 1777 - 1789
Main Authors: Liboiron-Ladouceur, O., Shacham, A., Small, B.A., Lee, B.G., Wang, H., Lai, C.P., Biberman, A., Bergman, K.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01-07-2008
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband semiconductor optical amplifier switching nodes and is capable of successfully routing multichannel wavelength-division multiplexing packets while maintaining practically error-free signal integrity (BER < 10 -12 ) with median latencies of 110 ns. Packet contentions are resolved without the use of optical buffers via a distributed deflection routing control scheme. The entire payload path in the optical domain exhibits a capacity of nearly 1 Tb/s. Further experimental measurements investigate the OPS interconnection network's flexibility and robustness in terms of optical power dynamic range and network timing. Subsequent experimental investigations support the physical layer scalability of the implemented architecture and serve to substantiate the merits of the data vortex OPS network architectural paradigm. Finally, modified design considerations that aim to increase the network throughput and device-level performance are presented.
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ISSN:0733-8724
1558-2213
DOI:10.1109/JLT.2007.913739