Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

• Published in: IEEE access Vol. 9; pp. 20575 - 20601
• Main Authors: Freire, Igor, Novaes, Camila, Almeida, Igor, Medeiros, Eduardo, Berg, Miguel, Klautau, Aldebaro
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Clock synchronization; Clocks; Delays; Field programmable gate arrays; Global navigation satellite system; Hardware; IEEE 1588; partial timing support; precision time protocol; Protocols; Synchronization
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3054164

This work explores clock synchronization algorithms used to process timestamps from the IEEE 1588 precision time protocol (PTP). It focuses on the PTP-unaware network scenario, where the network nodes do not actively contribute to PTP's operation. This scenario typically imposes a harsh environment for accurate clock distribution, primarily due to the packet delay variation experienced by PTP packets. In this context, it is essential to process the noisy PTP measurements using algorithms and strategies that consider the underlying clock and packet delay models. This work surveys some attractive algorithms and introduces an open-source analysis library that combines several of them for better performance. It also provides an unprecedented comparison of the algorithms based on datasets acquired from a sophisticated testbed composed of field-programmable gate arrays (FPGAs). The investigation provides insights regarding the synchronization performance under various scenarios of background traffic and oscillator stability.