Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 4; pp. 932 - 945
• Main Authors: Yoshioka, Kentaro, Saito, Ryo, Danjo, Takumi, Tsukamoto, Sanroku, Ishikuro, Hiroki
• Format: Journal Article
• Language: English
• Published: IEEE 01-04-2015
• Subjects: Ash; Binary search ADC; Clocks; Computer architecture; Delays; dynamic architecture and frequency scaling (DAFS); flash ADC; Frequency conversion; high-speed; Power demand; power scaling; subranging ADC; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2387191

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.