First Demonstration of a Logic-Process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications

• Published in: IEEE electron device letters Vol. 39; no. 9; pp. 1445 - 1448
• Main Authors: Seo, Myungsoo, Kang, Min-Ho, Jeon, Seung-Bae, Bae, Hagyoul, Hur, Jae, Jang, Byung Chul, Yun, Seokjung, Cho, Seongwoo, Kim, Wu-Kang, Kim, Myung-Su, Hwang, Kyu-Man, Hong, Seungbum, Choi, Sung-Yool, Choi, Yang-Kyu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-09-2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitors; Computer simulation; Digits; ferroelectric FET; Ferroelectric materials; Ferroelectricity; FinFET; FinFETs; Iron; Junctionless FET; Logic gates; Neural networks; neuromorphic computing system; Neuromorphics; Pattern recognition; Resistance; synapse; Synapses
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2018.2852698

A highly scalable synapse device based on a junctionless (JL) ferroelectric (FE) FinFET is presented for neuromorphic applications. The synaptic behaviors of the JL metal-ferroelectric-insulator-silicon FinFET were experimentally demonstrated after verifying the ferroelectric characteristics of the HfZrO X (HZO) film using a metal-ferroelectric-metal capacitor. The fabricated synapse showed distinguishable polarization switching behaviors with gradually controllable channel conductance. From neural network simulations using the proposed JL FE FinFET as synapses, the pattern recognition accuracy for hand-written digits was validated to be approximately 80% for neuromorphic applications.