An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron

• Published in: Neurocomputing (Amsterdam) Vol. 99; pp. 570 - 574
• Main Authors: Horita, T., Takanami, I.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01-01-2013; Elsevier
• Subjects: Applied sciences; Artificial intelligence; Coding, codes; Computer science; control theory; systems; Computer systems performance. Reliability; Connectionism. Neural networks; Electronics; Exact sciences and technology; Fault tolerance; FPGA; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); Multilayer perceptron; Neuron fault; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Software; Telecommunications and information theory; VHDL; Weight fault; Fault tolerance; Multilayer perceptron; VHDL; FPGA; Neuron fault; Weight fault; Hardware description languages; Description language; Field programmable gate array; Neural network; Error detecting code; Gene; VHDL language; Multilayer perceptrons; Error correcting code; Feedforward; Artificial intelligence; Fault tolerant system
• ISSN: 0925-2312; 1872-8286
• DOI: 10.1016/j.neucom.2012.07.001

A digital multilayer perceptron (DMLP) which is tolerant to simultaneous weight and neuron faults is implemented in an FPGA, where the weight faults are assumed to be between the hidden and output layers and the neuron faults are assumed to be in the hidden and output layers. In the implementation, a multilayer perceptron (MLP) trained by the deep learning method [1] is used to cope with the weight faults and the neuron faults in the hidden layer, and an error detecting and correcting code SECDED is used to cope with the neuron faults in the output layer. The implementation process named “FTDMLP-gene” is proposed which consists of three parts; the deep learning method, the VHDL source file generator and the outline of VHDL notation which describes an FTDMLP (fault-tolerant DMLP). The fault-tolerant ability of the FTDMLP implemented is shown. Further, The FTDMLP and the corresponding non-fault tolerant DMLP are compared in terms of hardware size, computing speed and electricity consumption.
This paper is the extension of [2,3].