Modeling and Design of FTJs as Multi-Level Low Energy Memristors for Neuromorphic Computing

• Published in: IEEE journal of the Electron Devices Society Vol. 9; pp. 1202 - 1209
• Main Authors: Fontanini, Riccardo, Segatto, Mattia, Massarotto, Marco, Specogna, Ruben, Driussi, Francesco, Loghi, Mirko, Esseni, David Esseni
• Format: Journal Article
• Language: English
• Published: New York IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Charge carrier processes; charge trapping; Depolarization; depolarization field; Dielectrics; Ferroelectric tunnelling junctions; Ferroelectricity; Memristors; Modelling; Neuromorphic computing; Neuromorphic engineering; Resistance; Silicon dioxide; Steady-state; Trapped charge; Tunneling; tunneling electron resistance
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2021.3120200

An in-house modeling framework for Ferroelectric Tunnelling Junctions (FTJ) is here presented in details. After a precise calibration again experiments, the model is exploited for an insightful study of the design of FTJs as synaptic devices for neuromorphic networks. Our analysis explains and addresses the tradeoff between the reading efficiency and the effects of the depolarization field during the retention phase. The reported results show that a moderately low-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> tunnelling dielectric (e.g., SiO 2 ) can increase the read current and the current dynamic range. The study shows also how the contribution of trapped charge may favor the stabilization of the polarization inside the FTJ, but also reduces the maximum read current.