High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip

• Published in: IEEE journal of selected topics in quantum electronics Vol. 16; no. 1; pp. 6 - 22
• Main Authors: Lee, B.G., Biberman, A., Chan, J., Bergman, K.
• Format: Journal Article
• Language: English
• Published: IEEE 01-01-2010
• Subjects: Architecture; Channels; Charge injection devices; circuit switching; Communication switching; computer networks; Dynamics; Energy efficiency; Modulators; multiprocessor interconnection; Network-on-a-chip; Networks; Optical modulation; optical resonators; photonic switching systems; Photonics; Semiconductor device measurement; Silicon; Space technology; supercomputers; Switches; Switching theory; Wavelength measurement
• ISSN: 1077-260X; 1558-4542
• DOI: 10.1109/JSTQE.2009.2028437

The stringent on- and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an energy-efficient manner. Here, experimental measurements on fabricated silicon photonic devices verify a large set of the components needed to construct these networks. The proposed system architecture is reviewed to motivate the demanding performance requirements of the components. Then, systems-level investigations are delineated for multiwavelength electrooptic modulators and photonic switching elements arranged in 1 × 2, 2 × 2, and 4 × 4 formations. Compact (~10 ¿m), high-speed (4 Gb/s) modulators, having a large degree of channel scalability (four channels demonstrated), are demonstrated with excellent data integrity (bit error rates (BERs) <10 -12 ). Meanwhile, switches are shown to transfer extensive throughput bandwidths (250 Gb/s) with fast switching speeds (<1 ns) and sufficient extinction ratios (>10 dB). Data integrity is also verified for the switches (BERs < 10 -12 ) with power penalty measurements amid dynamic operation. These network component demonstrations verify the feasibility of the proposed system architecture, while previous works have verified its efficacy.