Incremental fault diagnosis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 2; pp. 240 - 251
• Main Authors: Liu, J.B., Veneris, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit faults; Circuit simulation; Circuit testing; Explosions; Failure analysis; Fault diagnosis; Fault location; Logic testing; Manufacturing processes; open-interconnect; Very large scale integration; very large scale integration (VLSI)
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2004.841070

Fault diagnosis is important in improving the circuit-design process and the manufacturing yield. Diagnosis of today's complex defects is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations and fault models. To tackle this complexity, an incremental diagnosis method is proposed. This method captures faulty lines one at a time using the novel linear-time single-fault diagnosis algorithms. To capture complex fault effects, a model-free incremental diagnosis algorithm is outlined, which alleviates the need for an explicit fault model. To demonstrate the applicability of the proposed method, experiments on multiple stuck-at faults, open-interconnects and bridging faults are performed. Extensive results on combinational and full-scan sequential benchmark circuits confirm its resolution and performance.