VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

• Published in: IEEE transactions on semiconductor manufacturing Vol. 21; no. 1; pp. 3 - 13
• Main Authors: Sarangi, S.R., Greskamp, B., Teodorescu, R., Nakano, J., Tiwari, A., Torrellas, J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-02-2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Clocks; Design. Technologies. Operation analysis. Testing; Electronics; Error analysis; Errors; Exact sciences and technology; Failure rates; Frequency; Integrated circuits; Integrated circuits by function (including memories and processors); Mathematical models; Microarchitecture; Microprocessors; Power system modeling; Process design; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Statistics; Temperature; Time measurements; Timing; Voltage; High performance; Die; Frequency dependence; Processor; Integrated circuit; Error function; Microprocessor; Clock; Failure rate; Addressing
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2007.913186

Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.