Fault diagnosis and logic debugging using Boolean satisfiability

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 10; pp. 1606 - 1621
• Main Authors: Smith, A., Veneris, A., Ali, M.F., Viglas, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Boolean functions; Boolean satisfiability debugging; Circuit faults; Debugging; design errors; diagnosis; Engines; Fault diagnosis; faults; Logic design; Robustness; Runtime; Sequential circuits; verification; Very large scale integration; VLSI
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.852031

Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scale-integration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.