Fast Polar Decoders: Algorithm and Implementation

• Published in: IEEE journal on selected areas in communications Vol. 32; no. 5; pp. 946 - 957
• Main Authors: Sarkis, Gabi, Giard, Pascal, Vardy, Alexander, Thibeault, Claude, Gross, Warren J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; Channels; Complexity theory; Construction; Decoders; Decoding; Field programmable gate arrays; Hardware; Maximum likelihood decoding; Parity check codes; polar codes; Reliability; storage systems; successive-cancellation decoding; Systematics; Throughput
• ISSN: 0733-8716; 1558-0008
• DOI: 10.1109/JSAC.2014.140514

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.