Hot-Carrier Instability of nMOSFETs Under Pseudorandom Bit Sequence Stress
Hot-carrier instability under stress conditions emulating a random logic operation (random ON and OFF) has been investigated using pseudorandom bit sequence (PRBS) stress patterns. Furthermore, the impacts of PRBS stress on circuit-level operation have been compared with the conventional dc (static)...
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Published in: | IEEE electron device letters Vol. 37; no. 4; pp. 366 - 368 |
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Main Authors: | , , , , , |
Format: | Journal Article |
Language: | English |
Published: |
New York
IEEE
01-04-2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects: | |
Online Access: | Get full text |
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Summary: | Hot-carrier instability under stress conditions emulating a random logic operation (random ON and OFF) has been investigated using pseudorandom bit sequence (PRBS) stress patterns. Furthermore, the impacts of PRBS stress on circuit-level operation have been compared with the conventional dc (static) and ac (periodic) stress conditions using hot-carrier-induced random timing jitter. It was observed that the recovery achieved by charge trapping and detrapping under dynamic stress conditions significantly affects the degree of hot-carrier degradation. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2016.2533568 |